The sample is actually scheduled from the trailing edge of the cyan trace. This measures as 82 uSec. Which is a shift from the 40 uSec used at 4.4kHz. I hope there is enough time for the injected conversion to complete before the resolver code reads the value on the rising edge of the cyan trace.
Fixing up the filter has improved the output from the resolver markedly though.
I've mounted the resolver in my motor but it just produces garbage data until I fix the timing. The ADC is very noisy on the V1 board too (as previously noted). I measured 250mV ripple on the VDDA pin without a functioning gate driver PSU.