Switched ADC BMS

[anguicito]

OK 56 V How much I A Max?

[johu]

OK 56 V How much I A Max?

Uh, could you cut down the length of your sentences Seriously, what on earth are you asking?

Ok, back on topic. I have just pretty much decided that I will put a host processor on each module. It is just too painful with the differential i2c. I will reuse an addressing scheme I used earlier. Since now there will only be CAN and supply voltage on the cat5 cable 4 pins are left per RJ45 connector. So now one connector is the input, one is the output. The input receives a module address and sends it to the output + 1. Will be pulled down so the first module can have those 4 pins floating and be module "0".

The host processor will likely be an STM32F030C8T6 which is a basic part on jlc and costs $1. It also allows for some temperature sensor inputs and a current sensor input.

They will probably run a unified software and module 0 takes over some master functions for system integration, such as SoC and power limit calculation.

I won't add any traditional IO such as relays or miscellaneous inputs

[johu]

Finally had some time to work on the BMS again. I have removed all primary side logic and connected the isolators directly to an STM32.

The I2C peripheral can't be used as (it's quite broken in the STM and) SDA is split into a TX and RX line by the isolator where normally it is one shared line. Yes I could use an I2C isolator or I2C splitter but then I'm tied to some specialized (and expensive) IC again that I'm trying to avoid for resilience reasons.

So I'm running I2C with the SPI peripheral. It's pretty ugly, I have to bitbang the start sequence and address byte. Also the ACK bits need to be inserted requiring a lot of shifting. I'll also try sync serial or serial with a timer. On the other hand now that I've done the work I might as well leave it like this.

Also the balancing circuit runs nicely, I can either draw around 40mA from a connected cell or feed some (yet unknown) current to it.

Other quirks are switching the multiplexer. I'm using the MSB for clocking the shift register to the output register. That works great when the shift register is empty but causes glitches when something is already in there. So either I'll add a dedicated latch signal (which would require a second isolator) or think of something cleverer.

Another improvement could be the attenuation for the ADC. It ranges from -2V to +2V. Remember odd cells deliver a positive voltage, even cells a negative one. So I need to divide from, say, 4.5V to 2V and -4.5V to -2V respectively. Right now I'm using a simple resistive divider (10k from both polarities and 15k across the ADC input) but it loads down the mux mosfets and slightly distorts the reading. This could also be temperature dependent.

How can I do "active" attenuation (opamp) with a single 5V supply rail?

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[johu]

Glitchy mux issue solved:

QH' which is internally connected to the last bit of the shift register also provides the RCLK that latches shifted data to the outputs, as before. It means you always need to set the MSB to 1. Now the same signal is inverted and slightly delayed via a mosfet for the /SRCLR pin that clears ONLY the shift register when pulled low. Outputs remain untouched. Clearing the shift register also resets QH' so the reset signal self-releases.

[bexander]

Another improvement could be the attenuation for the ADC. It ranges from -2V to +2V. Remember odd cells deliver a positive voltage, even cells a negative one. So I need to divide from, say, 4.5V to 2V and -4.5V to -2V respectively. Right now I'm using a simple resistive divider (10k from both polarities and 15k across the ADC input) but it loads down the mux mosfets and slightly distorts the reading. This could also be temperature dependent.

How can I do "active" attenuation (opamp) with a single 5V supply rail?

To me, it is impossible to make a opamp output a voltage outside of its supply voltage.
Can't you just use higher impedance, say 100k or 500k resistors for the voltage division? What is the input leakage current on the ADC and is this leakage current constant so that the error it causes can be adjusted for?

[Pete9008]

There are diff amp configurations that could do it but the cheap ones don't have the accuracy and the good ones are expensive. Bexander's suggestion on the impedances is the first thing to check to see if that can get you a good enough compromise on accuracy. Putting a cap across the ADC input can sometimes help here as it allows higher series drive resistance while still being able to drive the ADC sampling capacitance.

Edit - just had a look at the datasheet and that chip has quite a complicated input sampling (it seems to module the sampling capacitor to give the PGA) so without a lot more thinking about it I haven't a clue what you could get away with

Also and saw this:

The absolute voltage range on each of the differential input pins is from VSS-0.3V to VDD+0.3V. Any voltage above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes atthe input pins. This ESD current can cause unexpected performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 “Electrical Characteristics” and Section 4.0 “Description of Device Operation”.

Are you sure it copes with the negative inputs OK, are both voltages allways within the Vss to Vdd range?

[johu]

Ah yes, I put a 1uF cap across the ADC now. Sampling cap if 3.2pF and impedance is 2.25 MegOhm (http://ww1.microchip.com/downloads/en/d ... 22003e.pdf). So upping the resistors should help.

To my surprise the latest measurement shows no voltage drop while it was 2mV on my first tests, without the capacitor across the ADC. Interesting.

[Pete9008]

Oops see edit above!

That makes sense, the cap provides the charge for the sampling cap. Without it the resistors do which gives the voltage drop across them.

Edit - to be clear, without the cap the resistors have to charge the sampling cap causing a voltage drop across them. With the cap the cap charges via the resistors and as long as enough time has been allowed the current will have dropped to zero by the time the conversion sampling starts so no voltage drop. The remaining error is the charge transfer between the two caps, with 1u and 3p it should be around the 18bit level.

[johu]

Just started experimenting with the mux actually cycling. So 1uF doesn't work as there is always a polarity change between adjacent channels. Of course the sequence could be changed. Anyway, It takes a long time for the new value to settle. Now I put in 1nF because that's all I have in my limited exile lab. Now edges look nice and sharp.

[johu]

Here is a plot from 14-bit, 60 SPS mode

I set Analog Discovery to generate 2.5V and 5V. As you can see it is rather stable and only jitters 0.5mV.
I can add my SMPS as a third voltage but it jitters quite a bit.

Still useful to test the balancing feature, that's how I know it draw 40mA.

Also connected a camera battery to the 1st channel so I could actually put some energy into it. Current draw on the DC-DC converter rose by around 20 mA, so only putting in like 15 mA or so. It is via two 47R resistors, so (5V-3.8V)/94=13mA -> adds up. Maybe I could use some lower value resistors to make this a bit more effective.

Voltage reading was also dead stable. Of course as soon as you run any balancing the reading becomes useless. So balancing must be released from time to time to get a valid voltage reading.

EDIT: here's how it works

[johu]

I tried using usart with clk but that's not going anywhere. For one the bit order is reversed (LSB first) and the start bit causes an unwanted start condition before every byte:

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So I'll stick with I2C over SPI for now. Or completely bitbang.

EDIT: just realized the STM32F030 has a newer SPI peripheral that can transfer all frame sizes between 4 and 16 bits. So by selecting 9 bits I should be able to do away with all the manual shifting.

EDIT2: Nooooo! the F030 doesn't have CAN. Maybe that's why it is so cheap. Back to F1 then? Don't feel like a major architecture change, but any cheap STM32 WITH CAN is fine

[mackoffgrid]

When / If the chip shortage comes to an end, the stm32F042 should be the cheapest. If you've stated this before then I apologize

[johu]

Not a bad call, just 32k of flash make me a little nervous, with boot loader and all that.

[johu]

Rolling with the STM32F103C8T6 now

Just basic functionality now. Need to add
- address lines for detecting position on bus
- analog input for current sensor single ended and differential
- 2 inputs for temperature sensors
- Some leds

[JockE28]

Looks great very nice job.

I'm still in a steap learning curve of this and working slowly towards my goal (build my own superEV) ~ 340hp 900 pound EV

I'm very interested to test this when I'm that far with my project, currently waiting for m3 rear DU and battery moduels

Ideas/questions

The pack moduels that I'm waiting for is configured 2p7s,
7 of those
Then I guess I would need 4 of these slave boards?

- Possible for master to output max charge/disscharge current from cell data curve (e.g temperature and SOC) to motorcontroller and charger/fast charger?

- control strategy for cooling/heating of pack for charge/discharge

- internal resistance measurement?

- this is awesome


Excuses for bad English writing skills and my total lack of knowledge
And thanks for your contributions to this community

[johu]

Hah, yes, corner case. 3 for 48, 4 for 49. No such thing as "slave boards". They are all identical, just one will take the function of the main node.
Yes the software will have some configurable curves for charge and discharge power depending on SoC, cell voltage and temperature.

Cooling/Heating not for now, internal resistance maybe as a by-product, i.e. calculating change in voltage as a reaction to change of current. I know there are some ways to inject some high frequency, could be done with the balancer circuit. But not planning for that right now.

I have added programming headers now and am running out of space for current and temp sensor connector:

So I might get rid of the RJ45 connectors and do screw or crimp terminals instead
Here's what we need:
- CANH/CANL
- GND/12V
- Activation signal that wakes up the BMS
- Addressing mode signal
- Current sensor 5V/GND/Out+/Out-
- Temp sensor 1 and 2 signal/GND
That is 14 signals on a screw terminal block or 20 on crimp terminals with pass through to the next board.

[johu]

3.81mm Phoenix for connections going through, can be combined with screw or clamp terminals. Current and temperature sensor via Molex.

Could make the cell tap inputs single row Molex as well

[JockE28]

Oh. Nice update!

Is there a maximum pcb size that you are stuck with?

As you are running out of space?

[johu]

Good question! No, just want to keep it compact

[JockE28]

Ah understandable.

Progress looks great so far

[johu]

Another early forum release


Just had 10 of these quoted at JLC and they go for around 20€ each without connectors and shipping

[JockE28]

Wow! Interesting. I live in Sweden, where re you located? What brings you here?

You can sign me upp for 4pcs

[JockE28]

Oh, one more thing that my brain is trying to understand.

Once you bleed one cell, this will go to waist through a resistor. It can't be used to another cell that needs it?

Forgive me for being a slow learner

[johu]

Once you bleed one cell, this will go to waist through a resistor. It can't be used to another cell that needs it?

I thought about placing an elcap on there and then rapidly switch between a cell that has excess charge and one that has too little. But there is so little charge being transferred that I dropped this idea. You could still have a strategy where you only ever charge low cells and never bleed any. Then energy would be transferred from the whole pack through your DC/DC converter into low cells. But it's not like there's a whole lot to gain...

Wow! Interesting. I live in Sweden, where re you located? What brings you here?

You can sign me upp for 4pcs

Cool, whereabout? I'm in Börtnan/Jämtland because we like it

[JockE28]

I thought about placing an elcap on there and then rapidly switch between a cell that has excess charge and one that has too little. But there is so little charge being transferred that I dropped this idea. You could still have a strategy where you only ever charge low cells and never bleed any. Then energy would be transferred from the whole pack through your DC/DC converter into low cells. But it's not like there's a whole lot to gain...


Cool, whereabout? I'm in Börtnan/Jämtland because we like it

Ah, i see. Just thought that no waste is for the better, but seems to work just fine in all other applications, so no need to make things complicated then it is

Jämtland is nice, real winter there.

I live closer to the equator, Falkenberg Hallands län, less winter