Switched ADC BMS

[johu]

This morning I made the decision I will just add around 10 Ohm series resistance on each input. Then even if there is a glitch it will be limited to a few 100 mA. It's a rather pragmatic solution but as it seems to only be a power-on problem I think it is appropriate.
I might also lower the gate resistors somewhat.

[johu]

And just discovered another issue:

This is the voltages of my 40Ah ESS pack. When I installed the BMS 7 weeks ago, the delta was 5 mV. Now it is more like 50 mV.

I think this is caused by the resistive dividers of the mux being on there 24/7. The lower the cell, the more often will it see the little drain. Would be less pronounced in a car with less uptime but still, a BMS should never contribute to disbalance. Amazing what many 10k of resistance can draw over time.

Argh

EDIT: makes we wonder, could the mux control also be floating... gotta think about this.

[johu]

I'm redoing the topology now. Each P-FET pair will have its own opto coupler controlled from the LV side. The STM32 is directly connected to the 3-to-8 decoders. Adds the optos (5 cts each) but makes 3 74HC chips and 18 N-Fets redundant. I'm keeping the decoders to have a degree of hardware protection against SW bugs.

[johu]

This would be the new mux design:

The two lower channels are NFETs and when turned on are connected to the cell 2 above it to always have sufficient gate voltage. The upper channels keep the PFETs that are pulled to the cell 2 below again fur sufficient gate voltage. This will draw an equal amount of current from all cells when doing a mux sweep, except the lower 3 cells. They deliver twice as much. I think I will compensate for that with lower pull down resistors on the upper channels.

And the according layout

[Jacobsmess]

Apologies for my ignorance on BMS type things, but will this be a flexible option to manage any homebrew battery packs up to certain cell amounts? Thanks

[uhi22]

Bipolar optos, with 10k load, can be quite slowly turn off, this needs to be considered for the blanking time. And maybe series resistors on the outp/outn would avoid smoke. And is it possible to place parts on the bottom side, to reduce the PCB size?

[johu]

Apologies for my ignorance on BMS type things, but will this be a flexible option to manage any homebrew battery packs up to certain cell amounts? Thanks

Yes, I already use it in that application (see my ESS thread under renewables)

Bipolar optos, with 10k load, can be quite slowly turn off, this needs to be considered for the blanking time. And maybe series resistors on the outp/outn would avoid smoke. And is it possible to place parts on the bottom side, to reduce the PCB size?

Yes, will make sure to insert like 50-100us of blanking time, not a lot compared to the 25ms sampling time per channel.
JLCPCB only allow one sided population, double sided should indeed make the board a lot smaller.
I'm SO sure that I will no longer have glitches now that I omitted the resistors - will regret later

I have also now gone over all mux states and calculated the total current draw through the pull-up resistors. The very first and very last channel see the least draw, also the 2nd one sees a bit less and the middle ones all have the same. I have changed the resistors to compensate for that, the upper-most channel needed an extra 2k4 resistor switched in to be on par. Now I'm at 54mAh/year between the cell that sees the least and the most draw (assuming 24/7 ontime)

[Jacobsmess]

Yes, I already use it in that application (see my ESS thread under renewables)

Thanks, would it be possible to setup to manage a 96s pack? I need a BMS system for my planned pack of 32 IPace modules (3S4P)

[johu]

Alright, alright, series resistors added

Thanks, would it be possible to setup to manage a 96s pack? I need a BMS system for my planned pack of 32 IPace modules (3S4P)

Yes, it is stackable. Gotta do a bit of testing with the latest revision to make sure it no longer blows up, then it's ready for sale.

[johu]

Took 5 days to put the cells back in balance:

[Proton]

@Johu

are you continuously balancing the cells? because that will imbalance the cells. For my solar system I have an active balance that can be setup when to start balancing. my cells are LiFePO4 3.2v and I setup the balance to start balancing only when cells reach 3.40v.

[johu]

I also start balancing above 3.8V, in that region soc/voltage curve is steep

[Proton]

LiFePo4 are full at 3.43V. but they can go to 3.65V. 3.4V / 3.65V = 93% charge.

Li-Ion 3.8V / 4.2V = 90% I think you can start at 3.9. But again, I only have experience with LiFe batteries.

Is this BMS going to work with LiFe Batteries ? I do not intend to ever use Li-Ion Batteries. The new Mercedes Sprinter coming this summer is going to use LiFe batteries.

[chentron]

johu, how much time for the birth ? days , weeks , months ?

[EV_Builder]

I also start balancing above 3.8V, in that region soc/voltage curve is steep

No so steep you mean?

[johu]

Is this BMS going to work with LiFe Batteries ? I do not intend to ever use Li-Ion Batteries. The new Mercedes Sprinter coming this summer is going to use LiFe batteries.

That is software-defined really. The ADC accuracy is high enough to do an open voltage estimate of SoC even for LFP batteries.

johu, how much time for the birth ? days , weeks , months ?

weeks, I think. New revision is currently on its way. If it's stable I could start selling boards. Software is not 100% there but good enough for tracking min/max cell voltage (and individual cell voltages of course) and Coulomb counting. Software is 100% open source so others can chime in
https://github.com/jsphuebner/FlyingAdcBms

No so steep you mean?

What I mean is at 3.6V recent NMC chemistry has a plateau, so 30% is 3.6V and 40% is 3.65V or something so 5 mV/%. Above 3.8V this becomes steeper, say 3.8V is 70% then 3.9V is 80% i.e. 10mV/%. So differences in top balancing are more visible in the upper voltage range.

[janosch]

I hope I will have time to contribute to the software side.

It will be a version of the chglim/dislim, built upon my thoughts here from December:
viewtopic.php?t=2861

[johu]

Yes, that would be great. Will come up with a list of things that I can think of.

I have received the new boards and hooked one up. Worked out of the box this time.
Next I will assemble a test battery to test two modules in cooperation. The thing that didn't work back in London.

STM32 had a little surprise for me: PB4 is tied to JRST (jtag reset). So you need to turn jtag off. But in order to do that you need to enable the AFIO clock. Took me a few moments to figure out...

[Proton]

I would love to buy and test one of those on my solar system. My current BMS is working perfectly but it has Bluetooth and I always have to use a phone with GPS enabled to see what is going one. Would be nice to replace that.

[johu]

I would love to buy and test one of those on my solar system. My current BMS is working perfectly but it has Bluetooth and I always have to use a phone with GPS enabled to see what is going one. Would be nice to replace that.

Sure, did you say you were going to order something anyway? Can just throw one in. WIP as always but certainly sufficient for obtaining min/max cell voltage over CAN

[johu]

Thought I'd just summarize current state of affairs and plans

EDIT: this will be maintained in the opening post viewtopic.php?t=2338

[Proton]

Sure, did you say you were going to order something anyway? Can just throw one in. WIP as always but certainly sufficient for obtaining min/max cell voltage over CAN

Unfortunately my order is already on the way.

[mackoffgrid]

And just discovered another issue:
grafik.png

This is the voltages of my 40Ah ESS pack. When I installed the BMS 7 weeks ago, the delta was 5 mV. Now it is more like 50 mV.

I think this is caused by the resistive dividers of the mux being on there 24/7. The lower the cell, the more often will it see the little drain. Would be less pronounced in a car with less uptime but still, a BMS should never contribute to disbalance. Amazing what many 10k of resistance can draw over time.

Argh

EDIT: makes we wonder, could the mux control also be floating... gotta think about this.

I don't see how this could be the problem unless your control mosfet is not off fully?

[johu]

I don't see how this could be the problem unless your control mosfet is not off fully?

The gates of the P-FETs are pulled to the voltage they are switching with a 10k pull-up resistor. E.g. gate of FET for V7 is pulled to V7. To turn on the gate is pulled to V0 by its N-FET companion via another resistor, say another 10k. So now current is circulating through two resistors pulling like 1mA from cells 0-7. It means cell 0 sees all turn-on currents, cell 1 sees 15 out of 16 and cell 15 sees just 1. You could say cell 0 sees a constant draw of 1 mA and cell 15 of just 1/16 mA. That's how they get disbalanced.

With the new topology that is mitigated.

Apart from that I just checked the displayed cell voltages against my multimeter and found cell 1 always reads 10 mV low. The others are correct.

[mackoffgrid]

The gates of the P-FETs are pulled to the voltage they are switching with a 10k pull-up resistor. E.g. gate of FET for V7 is pulled to V7. To turn on the gate is pulled to V0 by its N-FET companion via another resistor, say another 10k. So now current is circulating through two resistors pulling like 1mA from cells 0-7. It means cell 0 sees all turn-on currents, cell 1 sees 15 out of 16 and cell 15 sees just 1. You could say cell 0 sees a constant draw of 1 mA and cell 15 of just 1/16 mA. That's how they get disbalanced.

With the new topology that is mitigated.

Apart from that I just checked the displayed cell voltages against my multimeter and found cell 1 always reads 10 mV low. The others are correct.

Thanks, I misunderstood. The imbalance is not happening while the circuit is shutdown.