Tesla LDU Pick & Place File Fix? [SOLVED]

[nubster]

Hey everybody,

Trying to build my first LDU board here and ran into a couple of issues. Hoping someone can point me in the right direction.

I cloned johannes's repo and tried using the V6 files to order from JLCPCB. Due to a recent change on their side, the BOM file needed the Package column renamed to Footprint, which I easily addressed.

However, the pick & place file (CPL) does not render correctly in the preview. All the components seem to be off by a little bit, and some rotations are incorrect. I'm unsure if this is just a rendering issue or if the CPL actually needs to be updated. I tried editing the CPL file manually to see, and I was able to correct a few components, according to the preview, at least.

I am happy to contribute a PR to fix these minor issues, but I am unsure of the best way to fix the entire CPL. I tried opening the SCH file with KiCad, but I got an error saying it does not appear to be an Eeschema file, so is there another software I need to use? Should I write a Python script to fix it, as it's just a CSV file? What's the best approach? I am still relatively new to all this, so any help pointing me in the right direction is much appreciated. Thanks!

[royhen99]

The PCB layout tool is DesignSpark. Its placement file is not very compatible with JLCPCB. I have manunally adjusted the location and rotation in attached file. Check carefully as there could still be some mistakes. While doing that I noticed that the clearance between USART_RX and GND pin on STM32 was less than 0.1mm. I have corrected that and attached gerber files.

[johu]

The files are the result of my manual adjustment but I was less eager than royhen
Jlcpcb adjusts the placement, most of all they need to know polarity/pin1 of all components.

Anyway, thanks for posting the updates, will put them in the repo

[catphish]

It really bothers me that DesignSpark can't produce valid JLCPCB placement files, and I would be kinda embarrassed sending sending JLC a mess and expecting them to guess where everything should go. Also a big risk of orientations ending up incorrect.

Thanks royhen99 for posting corrected files.

This reply is more of a rant. I hope future designs can be done in Kicad which has a nice tool that spits out almost perfect JLC placement files (though be sure to fix the IC orientation with their GUI before finalizing.

I don't blame Damien for any of this of course, it's just bad luck that DesignSpark doesn't produce the right output. I've already pestered him enough to start using Kicad

[nubster]

You guys are the best, thank you!