That's brilliant feedback. Thanks! I'll include that in the docs shortly. It looks like that process and adapter would work just as great on Windows and Linux too.

I've just released v0.3.2 of the tool which has a minor fix:

What's New

Correctly display bitfield parameters with a zero value where a description is provided in the parameter definition.


This makes the output a bit more understandable for parameters with many possible failures I think ...

Meanwhile in Open Source development... I have finished making the updates to the Tesla M3 gate driver support code to pull out the detailed fault information:

https://github.com/jsphuebner/stm32-sine/pull/51

@crasbe was absolutely correct in their analysis as to the order in which replies are ...

AMP3R wrote: ↑Thu Jun 26, 2025 4:43 pm Do you have .bin dump?

No. You can run through a simple tool like xxd:

Damien has some captures of the EEPROM access with the Tesla firmware running:

https://github.com/damienmaguire/Tesla-Model-3-Drive-Unit/tree/master/EEPROM

You need Saleae Logic 1.x software to open these files.

I've attached a dump I made of my EEPROM before I started writing to it. It's mostly ...

Managed to get my JTAG connection working again so I can make some improvements to the Tesla M3 gate driver support:

https://github.com/davefiddes/stm32-sine/tree/m3-gate-driver-improvements

So far I've included the various fixes from above and a new version of the gate driver class. This has a ...

That wasn't my understanding. The way they seem to work is that the commands are processed by the first chip in the chain. If the command is valid (using the CRC I think) the first chip then passes through subsequent bits to the next chip in the chain. The process resets when the ~CS~ pin is ...

Progress.

At 3.507s in the trace it looks like the DESAT flag is triggered on the even gate drive chips which should be all the high-side drivers (U293, U292 and U291 on the Tesla board). Everything else looks OK.

You should see PWM coming out of the low-side.

I'll try and find some time to write ...

All looks happy (really this time) assuming no fault errors being logged.

Amusingly you can see in the trace just how hard the STM32F1 has to work when generating PWM as there are some odd looking gaps between writes to the chips. This is fine by the protocol as I understand it, it's just the ...

That's correct. I have not had much sleep. I think I need a break.

Edit: One thing I remember from my earlier works with these chips is that the Don't Care bits in the status often assume random values and have to be masked off. The code deals with this but any manual analysis has to also take this ...

Clock looks sensible now. I'm still seeing odd values in the SPI decode. For example at 1s 854ms the driver is trying to send 0x9DD6 six times to write CFG2 register but this is decoding as 0x0DD6 and 0x1DD6 sometimes. From the behaviour this looks to be a capture artifact.

From what I can gather ...

I think I've figured out what's going on. The SPI bus is running a bit too quickly. It has to be under 5MHz.

If you modify spi_setup_teslam3() and swap the parameter passed to spi_init_master() from SPI_CR1_BAUDRATE_FPCLK_DIV_8 to SPI_CR1_BAUDRATE_FPCLK_DIV_32. I think this will make it run at 3MHz ...

Bother. That's quite a complete failure. You'll need to trace through the initialisation code to figure out which bit it is getting upset by. An SPI capture might be necessary to verify that data is going into and then out of the SPI chain. It should look like the captures you took way back on the ...

Hmm. That's unfortunate. Maybe it'll be fine with the correct config loaded. My driver code will need a bit of work to get useful debug info out of it beyond "There is a fault". Hopefully that won't be required.

Every day is a school day it seems. Didn't know you could run the gate drivers without any config but the DS confirms this.

I've checked against your latest schematics and the code in the MG_DU branch stands, nothing has changed with the SPI and SD control that would break it that I can see. I don ...

All gate drivers powered up, reset and waiting for spi configuration to be loaded.


Um. I dont think you need to be worrying about the spi configuration. That's looks to be all in place and working. Those chips are generally very unhappy until properly initialised with a working isolated gate ...

I don't think I'd seen anyone say that the front drive unit used IGBTs before. If anyone harbours a desire to run this with Damien's board it would be useful to get an SPI capture of the gate driver initialisation sequence before removing the Tesla PCB from the rest of the inverter. It doesn't need ...

I've just released v0.3.1 of the tool:

What's New

Include support for serial and slcan python-can drivers by default
Update README with details of working and not working Windows CAN interface
adapters


The good news is that I've found a CAN adapter that works very reliably in Windows (and ...

Interesting experiments with conformal coating. I saw a video about someone repairing a potted hybrid module in an old computer the other week using regular paint stripper (with dimethoxymethane) and wondered if this approach might work on Telsa board but didn't want to experiment as I'd really ...

Don't worry about asking, you weren't to know it was going to be quite as frustrating as it turned out. Having slept on it, unsurprisingly, I have ideas for a way forward...

Had a very frustrating day trying to get this to work on Windows 11 (10 should be the same). The TLDR version is that it doesn't at the moment. For the time being I'd recommend using a Linux virtual machine and pass-through the USB CAN adapter to the VM. VirtualBox is your best bet on Windows 10 ...

If the "oic" command isn't available that sounds like where it is installed to is not on the path. To help out it would be useful to know the platform you are using and the output of the install command. It would also be helpful to know the CAN adapter you would like to use with it.

I've just released v0.3.0 of the tool:

What's New

Log symbolic values for enum and bit-field params by default. The old behaviour can be re-enabled with the "--numeric" option.
Add a "listparam" command to explain a single parameter.
Add a "--debug" option to all commands to allow problems to ...

Couple of comments on the video:

Seems like the STGAP1BS could be pre-supplied to JLCPCB like the QCA7000 on the Foccci for production runs of your board. Sure it adds cost but reflect that in what you charge for the board. No such thing as a free lunch.

I can recommend the "Fabrication Toolkit ...

They have had fun. Looks like they've removed the HVIL current sense resistors. Couple of current sense resistor whose purpose I can't remember have gone too (maybe to do with the resolver exciter I think). CAN termination is gone on both busses I think. Who only know what the forest of footprints ...