SciroccoEV wrote: ↑Mon Sep 26, 2022 1:19 pm
Blanking time, even more so than rise and turn-on times will vary. If one stage trips before the other, there's no advantage to the second stage.
Parallellng the stages is thermally advantageous, but if the problem is a motor with very low inductance and therefore very fast rise of current, then tripping may be a problem.
This may not be the cause of the trips, I'm just trying to explain why paralleling the satges may not be of any help.
Thanks for explaining, I think I understand what you're getting at now.
The desat blanking time will be a little variable but it has to be good enough to prevent false trips on the slowest 'normal' IGBT, and fast enough to protect the device, otherwise there would be numerous nuisance trips.
Consider the case of two IGBTs with separate drive and desat detect circuits that are paralleled and are trying to drive a load that each individual device is not capable of driving by itself. One is slower than the other but both are fast enough to complete the switch before the end of the desat blanking time. What will happen is that the faster device will attempt to turn on but go into desat but since it is still within the blanking window the driver will not trip. The slower IGBT will then complete its turn on pulling the voltage across both IGBTs down below the desat threshold (still before before the end of the desat window). The end result is that the desat won't trip but the first device will have been operating unsaturated for a few micro-seconds and so will have dissipated more power than the other. Essentially it will be running with much higher switching losses and so will be running hotter.
Effects like the above are why I was particularly interested to see that there are individual temperature sensing diodes on each IGBT die and that each driver appears to have only a single error output opto. I think it is quite possible that the inverter is tripping out on over temperature on a single IGBT.
Regarding low motor inductance what would a low inductance value be, would 600uH be reasonable (I don't have a good feel for this yet)? If so then the current rise during an entire 113us pwm switching period would only be 66A (at 350V), the current rise during the IGBT switching time will be a tiny fraction of this.
Edit - this link has quite a good section on desat and blanking windows
https://www.ti.com/lit/eb/slyy169/slyy169.pdf (pages 29 and 30)
Edit2 - just did a quick sum, say the faster device is running unsaturated for 2us on each turn on, at 350A, dropping 100V at a pwm freq of 8800. That gives an increase in power dissipation of 600W. Say an inverter is 95% efficient at 100kW (is that reasonable?) so in normal operation each switch in the bridge will be dissipating a sixth of the loss, say 1% or 1kW. So the increased switching losses could mean that device dissipating around 60% more power than it's neighbours.
Edit3 - I don't believe the 2us example above is realistic. 1us or even 500ns would probably be more representative of typical behaviour on something like the Prius inverter.
Edit4 - The only way I can think of getting very high rates of change of currents is shoot through, @Bigpie, what deadtime are you using?