Switched ADC BMS

Topics concerning OEM and open source BMSes
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Great idea! Here's one that JLC populates at 3 cents : https://datasheet.lcsc.com/lcsc/1811091 ... C70065.pdf

So I'd place the TVS before the resistors then to provoke a high fault current and trip the fuse. At 900 mA this one will open after 10 ms.

The mux transistors support 8A pulse current and have 255 mOhm resistance. The fuse is 1.6 Ohm. So all in all 2.6 Ohm (4 transistors, 1 fuse). When shorting 65V into this we'd be at (65-5)/2.6=23A. Maybe 4P 22 Ohm resistors should be put in series for FET protection? Then it'd be 7.4A.

EDIT: might as well place the TVS across GNDA/VDDA so one 22 Ohm resistor and two body diodes limit the current to 136 mA@8V or 2.7A@65V. In the latter case the fuse would trip instantly, in the light overload case it would take about 0.5s
EDIT2: remains the question if the 22 resistor survives?
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

And here's my latest iteration of the mux power supply:
image.png
image.png (5.22 KiB) Viewed 3693 times
When the ADC power supply turns on it activates the photo coupler which enables the linear regulator. At an assumed 1 mA current draw Q24 needs to dissipate 62 mV when running off 67V (16x4.2)

EDIT: even more tightassed:
image.png
image.png (8.51 KiB) Viewed 3678 times
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
bexander
Posts: 834
Joined: Tue Jun 16, 2020 6:00 pm
Location: Gothenburg, Sweden
Has thanked: 63 times
Been thanked: 89 times

Re: Switched ADC BMS

Post by bexander »

I like the last one, very few componentes but don't you need to bias the Zener diode by placing a resistor between V16 and Zener cathode?
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

According to the simulation, no. I think the little PV cell inside switches on the transistor which pulls the emitter to V16 and thereby the base to E+0.7V. When base hits 5.6V the Zener starts counteracting the PV cell.
Also biasing the Zener would also bias the opto, turning it always on.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

I tested using the opto as voltage regulator and failed. The current generated by the PV cell in the opto is smaller than the Zener leakage current. So will need an external transistor after all.
Also I found there's no need to power the opto coupler from the DC/DC auf the ADC. It can just be turned on by the LV side, maybe even with a pin from the uC. This also puts it in a more convenient location on the PCB.

EDIT: also got to measure the mux power consumption. It draws 900uA at any voltage from 3-5V and the current does not rise when the mux is switching.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

New BMS boards arrived :)

Worked almost out of the box, just needed to stick a 1uF cap across the output of the new LDO. It doesn't like the cap being behind the opto coupler.
These boards will get a proper shakedown in the clipper taxi.

Other changes:
- ADC input/balancer now protected by TVS (maybe too high rating, saw voltage climb above 6V) and fuse
- Enable input doubles as 12V sense input. This also makes it easier to determine whether we're the first module in the row or subsequent one
- LED now connected to processor to give as the usual alive blink
- And again: mux now supplied by battery voltage instead of DC/DC converter

Mux supply draws 4 uA when dormant (quiescent current of LDO) and 1.4 mA when running.
Attachments
1681374527356.jpg
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

We did the first HV power up of the battery supplied mux yesterday and it did not go so well. While we successfully completed the test with one board running with all 3 boards first showed no voltages measured on 2 of 3. We then found the 5V supply of the mux had collapsed and on a second try we popped something.

Turns out all logic chips were fried, root cause to be determined. I think the LDO must have not regulated cleanly from 65V down to 5V. So we will revert that design change and populate the DC/DC converters.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

More digging. Turns out the LDOs work just fine, backed by the fact that we now also fried modules that used the DC/DC converter instead.

Next stop is the reset circuit. Basically after every control word reception the shift register in the 74HC595 must be reset to all 0s, otherwise random data is shifted through on the next reception. To cut it short this will switch on some random channel during the dead time where no channel is supposed to be on. No deadtime, as always, is bad and means pop.

We found that on some boards the reset circuitry, comprised of an N-channel fet with large gate resistor, would not reset. We installed lower value resistors, scope the reset signal carefully and all looked good. Tested on our test brick went fine, testing in the taxi as well. Until it no longer did. At some random point we got smoke again from the last module. The bottom most N-channel FET had a blow hole

Can think of 3 suspects:
- Bottom N-channel FET is actually two 2N7002 60V FETs in series (BOM consolidation). Maybe this series configuration can go wrong? Like one switching on before the other?
- The DC-DC converter has too much capacitive coupling?
- The reset circuitry stopped working midway

Anyone have experience with serial FETs? I'll now replace them with a single 100V one
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Can let the series fets off the hook. Replaced them by one larger 100V model and after a couple of power cycles it blew up again. The failure mode seems consistent: the lower fet is on while another higher fet on the same rail is also on. Exactly the condition to be avoided by the discrete logic. It becomes visible as it's always the same PCB trace that burns.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
uhi22
Posts: 554
Joined: Mon Mar 14, 2022 3:20 pm
Location: Ingolstadt/Germany
Has thanked: 83 times
Been thanked: 392 times

Re: Switched ADC BMS

Post by uhi22 »

Assuming, that the 1-out-of-16 selector logic is fine, I see two potential root causes, with dynamic nature:
(1) Cross-current due to switching one path active and the other passive at the same time. Especially the 10k gate-to-source resistors make the switch-off slow, and so the switched-on path already provides current, while the switched-off path is not yet really off. This leads to a short cross-current, which may lead to thermal stress, and if applied cyclically, to burning on of the FETs. Maybe this can be excluded, if the software anyway makes a "idle" in between of two channels, I did not look.
(2) The miller capacitance. If the U_GS is zero (caused by the 10k gate-source-resistor), and we apply a sharp edge voltage ramp at drain-source, we get a voltage also on the gate. Because the capacitance between drain and gate (miller) and between gate and source are forming a capacitive voltage divider. The 10k tries to keep the U_GS zero, but this is slow. With the values for the HSS2P10 (datasheet found here: http://www.hs-semi.cn/Uploadfiles/20210902132635976.pdf) I see 900pF C_GS and 43pF miller. As example, an edge from 0V to 40V on drain would lead to approx 43pF/(43pF+900pF)*40V = 1.8V. This is in the range of the threshold voltage (1V to 3V). If we have a exemplar with low theshold voltate (1V is still matching the specification), this situation would lead to significant current flow, until the 10k gets the situation under control. If this behavior is confirmed, a software-workaround could be to avoid jumping large steps in the accu chain, instead go small steps upwards and also small steps downwards, to avoid big jumps of the U_DS and so limit the back-coupled U_GS safe under the threshold voltage. A hardware improvement would be to add protection resistors (100ohm or so) between the mux transistors and the OUTP / OUTN rail, which limit the short but heavy cross-current-spikes.
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Awesome, thanks for your suggestions.
I found it's always the OUTN trace that burns, never UOUTP. Will add a picture later.
Also I said "at some random point" it goes wrong. That isn't correct, it always happens after power-up once the mux starts operating. AND it only happens when more than one module is used. With 1 module we can power cycle as often as we want and it's fine. With two modules it only takes like 3 power cycles until one of them fails. When putting just a dummy module in with no HV connection it has no influence, both must be connected to HV. What possible interaction could there be when the HV section is completely isolated?

What about changing the 10k turn-off resistors to a lower value (along with the turn-on ones, of course)?

Adding a resistor to each channel would be a bit painful in layout but certainly very safe. I wouldn't want to go higher than 10 Ohms though as otherwise the balancing becomes too slow.

Switching the mux in different order would be a nice software fix. Like doing all even ones when going up and then the odd ones when going down.

And finally, yes there is quite some blanking time between the switching (50 us iirc). I have attached a logic analyser to 16 out of 17 control signals and that works fine.

UPDATE: picture
1682956620771.jpg
It's always that trace that burns plus the low side mosfets are often killed but never the trace to them (the horizontal part of the burned track). Could either point to something meaningful or just means the weaker 2N7002 burn before the trace does.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Alright, some new findings
I have scoped the mux 5V supply (blue) which is switched on by the processor about 1s after power up. The other trace is the gate of Q18/Q26 (channel 6). We'd expect first the power-up and 150ms later turn on of channel 7, like so:
grafik.png
After doing many power cycles I got a picture like this:
grafik.png
I repeated it on channel 8 and found the same glitch at the same time.
I don't see the other channels but somehow I suspect they glitch as well.

And likewise on channel 0
grafik.png
I suspect they all glitch at the same time or at least there is a possibility they will. In any case the early turn-on is not supposed to happen. Will keep digging.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
uhi22
Posts: 554
Joined: Mon Mar 14, 2022 3:20 pm
Location: Ingolstadt/Germany
Has thanked: 83 times
Been thanked: 392 times

Re: Switched ADC BMS

Post by uhi22 »

Strange. So it means, that the 1-out-of-8 decoder randomly has (hopefully only) one output active after startup. This looks ugly, but still is no reason to burn anything, because it is just ONE, no current flow possible in the OUTN rail itself. I did not analyze the complete logic part, maybe the idea of "self-secure" is not fully realized, an a certain, random init pattern leads to activation of two pathes on OUTN.
User avatar
uhi22
Posts: 554
Joined: Mon Mar 14, 2022 3:20 pm
Location: Ingolstadt/Germany
Has thanked: 83 times
Been thanked: 392 times

Re: Switched ADC BMS

Post by uhi22 »

Another thing: As I understand the logic, the Y is always false, because it would be only true if (A XOR B) AND (A AND B), but either they are different to fulfill the XOR or they are both true, to fulfill the AND. Maybe I missed something or use an outdated version (it is from the beginning of the thread).
image.png
image.png (8.06 KiB) Viewed 3144 times
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Sorry, here is a more recent version (PS2 is not populated in case you wonder)
grafik.png
Meanwhile I found random output bits of the HC595 start out as one. Unfortunately there is no reset signal for them, only for the internal shift register. Like you say, that in itself doesn't present a problem, as the first control word that is sent after power-up disables all channels.

EDIT: G16 is a special case where the "even" decoder is disabled and the fet is switched by the AND gate instead
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

And early forum release because it may assist fault finding
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Just thinking, our power cycles were always rather short. What if the last control word gets preserved in the shift register and the power up reset (gone in above circuit) fails to clear it because too much charge is left in the cap. Then we would have the glitchy register behaviour once at startup where random bits are shifted through and latched. Still doesn't cause turn-on of two FETs logically but with the slow switching time could cause overlapping.

Maybe the decoder-disable bits should be held high with some circuit that doesn't fail to do so on a short power cycle.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
uhi22
Posts: 554
Joined: Mon Mar 14, 2022 3:20 pm
Location: Ingolstadt/Germany
Has thanked: 83 times
Been thanked: 392 times

Re: Switched ADC BMS

Post by uhi22 »

I could also imagine an out-of-sync issue between the 8 bits sent by the software, and the 8 bits in the shift register. E.g. by one extra clock cycle or one missing clock cycle (EMI, whatever) at the beginning, there is the risk that the shift register will not reset, because for resetting we need the Q7' at high for ~50µs. If the intended trigger bit is just shifted through, because there was one clock pulse to much, the next bit (lets assume it is zero) is on the Q7' when the transmission makes a pause, and no reset is done. I guess the single clock cycles are much faster than the reset filter time, so a 1 on the Q7' during the shifting will not reset. When the software sends the next 8 bits, still the same 0 at the same position comes to the Q7'. The 1s which are in the data stream will update the latch outputs, but not with the intended content, but just "random" patterns. This situation does not heal by itself, if we assume that the neighbor of the "trigger bit" is always zero.
In the end this effect would lead to switching between channels without blanking time, and the rest is known. If you still have some working boards, you could make a software which just makes switching between 2 and 16 or so, without blankout, and just make a nice macro video of burning PCB traces :-) Maybe someone wants to donate a thermal imaging camera, this gives nice pictures, too :-)
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

The SPI clock runs at 93 kHz so agreed at that rate a shifted "1" wouldn't cause a reset. On the other hand the traces are short and the isolator has a push/pull output.
A control word looks like this: 0x80Cx (x: channel number) shifted MSB first. I'd think when the 0x80 is shifted through fine, the blanking time is guaranteed.
Already thinking about putting a Padauk uC on there (10 cents) instead of all the logic chips. Would be cheaper, less troublesome, require less space. But is a single-source part and needs programming.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Attached the logic analyzer, here's the issue:
grafik.png
Switching from channel 6 (that happens to be in there) straight to channel 0 without blanking time.

UPDATE:
It seems indeed to be a function of the cycling time. So if you power down and 2s later power up again it seems the output latches of the SR are still in the state where they were turned off. If you wait like 10s the start up is normal. One solution would be to delay mux power-up by 10s in software. Bit of a workaround, a hardware delay might be nicer
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Alright, this might fix it:
grafik.png
When booting up the mux supply is off. Next the mux supply is turned on with the possibility of random data being in there. 25ms later (the power supply is stable by then) we shift 0x0080 through the register. The first 8 zeros clear whatever is in there, the 0x80 latches 0 to all output. 25ms later we actually start sampling.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
crasbe
Posts: 234
Joined: Mon Jul 08, 2019 5:18 pm
Location: Germany
Has thanked: 43 times
Been thanked: 97 times

Re: Switched ADC BMS

Post by crasbe »

johu wrote: Wed May 03, 2023 7:11 am Already thinking about putting a Padauk uC on there (10 cents) instead of all the logic chips. Would be cheaper, less troublesome, require less space. But is a single-source part and needs programming.
Why not go with what you already know and have and use a STM32F030 or STM32G030 in TSSOP-20/LQFP-32 or something like that? They are less than $1 on LCSC in quantity 1 and ~$0.50 in quantity 100+.

https://www.lcsc.com/product-detail/Mic ... 89040.html
https://www.lcsc.com/product-detail/Mic ... 29331.html

You can use your existing knowledge and toolchain, which saves you time in comparison to the Padauk chip (and realistically, the difference for 100 pieces would be 40€. That's less than 1h of your time :D )

Yes, they are single-source-ish as well, but so is the F103 that's on there anyway. (There are GigaDevices chips for TSSOP-20 and LQFP-32 as well, but I didn't check which ones would be compatible and which ones are not.)
AND if you do the programming for one STM32, you can do the programming for the second one quite easily too. :)
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Right, the F030 is even a basic part.
Will, see, if the latest finding isn't the root cause I might as well do that.
I do assume it will consume more than 1 mA though.
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
User avatar
crasbe
Posts: 234
Joined: Mon Jul 08, 2019 5:18 pm
Location: Germany
Has thanked: 43 times
Been thanked: 97 times

Re: Switched ADC BMS

Post by crasbe »

Yes, the F0-series isn't the greatest in terms of energy consumption, the L0-series would be a better choice. Some parts only use "88µA/MHz", which is obviously not a value to go by directly, but certainly a good ballpark value. Unfortunately all STM32L0 are extended parts at JLC, the cheapest one with enough GPIOs would be this: https://jlcpcb.com/partdetail/Stmicroel ... T6/C110878

I think the ones I linked before don't have enough GPIOs to replace the shift registers.
User avatar
johu
Site Admin
Posts: 5684
Joined: Thu Nov 08, 2018 10:52 pm
Location: Kassel/Germany
Has thanked: 153 times
Been thanked: 960 times
Contact:

Re: Switched ADC BMS

Post by johu »

Maybe some less consumption can be achieved with sleep modes. It's woken up by SPI clock (if possible), receives the data, sets pins and back to sleep.

I thought about above glitching a bit more. It is just an issue if after power-up a channel is selected without inserting a turn-off command.
But then we also tested with modules that have permanent 5V supply via DC/DC converter. They receive many mux-off commands during bootup. These blew up just as well. So I'm afraid the above isn't the solution either. Even more so as it wouldn't explain why one module works but stacking 2+ modules clearly triggers the blowup.

Could it be some capacitive current over the isolator or DC/DC converter?
Support R/D and forum on Patreon: https://patreon.com/openinverter - Subscribe on odysee: https://odysee.com/@openinverter:9
Post Reply