New BMS for bq76PL455A based batteries

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catphish
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

So, I've spent basically all day with the oscilloscope, an unmodified board, a 1m transmission line, and no noise. I've reached a few useful conclusions.

Firstly, the combination of driving the line at 3v3, and the 1nF capacitor is limiting the length of the transmission line to 1metre. At 1m, it works 100% of the time, if I extend it to 130cm, it only works about 1% of the time. When it fails, it is not the received signal that's weak, but rather no signal is received at all because the battery module is not receiving the request. This makes sense as the TI chip drives the line at 5v, so the transmitted 3.3v signal will be much weaker. It would have been good if I could've found a way to drive the line at 5v but I couldn't find a good way to interface a 5v line driver with the RP2040. I confirmed that the 1nF capacitor is a huge contributor to this limitation.

Secondly, I did exactly as you suggested, and used a side-set output to align my sample point with the signal. I discovered that my original code was in fact not out by a single cycle, but two cycles, putting it barely before the zero crossing! I have now moved it back to dead centre of the first half-bit. This made no difference at all to performance in my office, but will hopefully have an impact in a noisy environment.

I still have some tidying of the code to do, but it is my hope that this combination of the hardware changes already made (10nF cap, 100uH inductor, 10k resistors), the new sample point, and adding reties to the code, will improve matters dramatically. This has also been a good reminder that when it comes to installation, this really needs to be placed directly adjacent to the battery modules, as I have done in my own vehicle.

I have of course also taken on board your recommendation about trying to detect false starts. I havent worked out how best to implement this yet, but a simplistic approach might just be to take a single extra sample after the wait into a scratch register, then do a JMP based on the register value.

I will push the full reworked code shortly.
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

catphish wrote: Fri May 13, 2022 5:10 pm Firstly, the combination of driving the line at 3v3, and the 1nF capacitor is limiting the length of the transmission line to 1metre. At 1m, it works 100% of the time, if I extend it to 130cm, it only works about 1% of the time. When it fails, it is not the received signal that's weak, but rather no signal is received at all because the battery module is not receiving the request. This makes sense as the TI chip drives the line at 5v, so the transmitted 3.3v signal will be much weaker. It would have been good if I could've found a way to drive the line at 5v but I couldn't find a good way to interface a 5v line driver with the RP2040. I confirmed that the 1nF capacitor is a huge contributor to this limitation.
Thant's very interesting, I would have expected it to go quite a bit further. Do you know the length limit for a modified board? What's the cable - screened twisted pair?
catphish wrote: Fri May 13, 2022 5:10 pm Secondly, I did exactly as you suggested, and used a side-set output to align my sample point with the signal. I discovered that my original code was in fact not out by a single cycle, but two cycles, putting it barely before the zero crossing! I have now moved it back to dead centre of the first half-bit. This made no difference at all to performance in my office, but will hopefully have an impact in a noisy environment.
That's why I always do it, even if it's a pain to set up and I'm 90% sure it's right, more often than not it shows up a problem!

catphish wrote: Fri May 13, 2022 5:10 pm I have of course also taken on board your recommendation about trying to detect false starts. I havent worked out how best to implement this yet, but a simplistic approach might just be to take a single extra sample after the wait into a scratch register, then do a JMP based on the register value.

I will push the full reworked code shortly.
I'll look out for the new code. Think I know how to implement it having now read the data sheet and I'll try to post a modded version later today (apologies in advance as I'm sure there will be syntax errors as I don't have a compiler set up to check it)
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Sorry - based it on the old code as I wanted to get it done.

Code: Select all

.program daisychain_tx
.side_set 1
.wrap_target
  pull block            sideset 0 // Block until we get a word from the CPU, and put it on the shift register (ISR), meanwhile don't control the line
  irq set 4 
  mov pins, NULL [15]   sideset 1 // Wait a while, but start controlling the line (sideset)
  mov pins, NULL [15]   sideset 1 // Wait a while longer
  set y, 7              sideset 1 // Loop counter
  mov pins, ! NULL [4]  sideset 1 // Set data pin HIGH. This is the first half of the start bit
  mov pins, NULL   [3]  sideset 1 // Set data pin LOW. This is the second half of the start bit
bitloop:
  out x, 1              sideset 1 // Shift one bit off the ISR to register X
  mov pins, ! x    [4]  sideset 1 // Output inverse of x to the data pin
  mov pins, x      [2]  sideset 1 // Output x to the data pin
  jmp y-- bitloop       sideset 1 // Loop for 8 bits
  out x, 1              sideset 1 // Load bit 9, this is the framing bit, if it's set, we transmit HL, else we transmit nothing (LL)
  mov pins, x    [4]    sideset 1 // Send first half of final bit (a 1 in bit 9 activates the framing)
  mov pins, NULL [4]    sideset 1 // Last half of final but is always low. Add a short delay before wrapping and releasing the line
  irq clear 4
.wrap

% c-sdk {
static inline void daisychain_tx_program_init(PIO pio, uint sm, uint offset, uint datapin, uint enablepin) {
    pio_sm_set_consecutive_pindirs(pio, sm, datapin, 1, true);
    pio_sm_set_consecutive_pindirs(pio, sm, enablepin, 1, true);
    pio_gpio_init(pio, datapin);
    pio_gpio_init(pio, enablepin);

    pio_sm_config c = daisychain_tx_program_get_default_config(offset);
    sm_config_set_sideset_pins(&c, enablepin);
    sm_config_set_out_pins(&c, datapin, 1);
    sm_config_set_out_shift(&c, true, false, 9);
    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
    sm_config_set_clkdiv(&c, 2);
    pio_sm_init(pio, sm, offset, &c);

    pio_sm_set_enabled(pio, sm, true);
}
%}

.program daisychain_rx
.wrap_target
beginning:
  wait 1 pin 0          // Wait for data input to go high
  wait 0 irq 4          sideset 1 // Wait till Tx routine is inactive
  jmp pin beginning     // Loop back to igore the data if invalid start bit, if Tx was active (but now inactive) should also jump
  jmp pin beginning     sideset 0 // Loop back to igore the data if invalid start bit
  nop               [9] // Skip the first bit - reduced by 3 for above and by one to move first sample 1 clock early, increased by 5 to read 2nd half
  set y, 7              // Loop counter
bitloop:
  in pins, 1            sideset 1// Put the bit into the OSR
  in pins, 1            // Put the bit into the OSR
  in pins, 1        [6] sideset 0// Put the bit into the OSR
  jmp y-- bitloop       // Loop 8 bits

  in x, 1               sideset 1// Put the framing bit into the OSR
  in x, 1               // Put the framing bit into the OSR
  in x, 1               sideset 0// Put the framing bit into the OSR
  in null, 5            // Dump 5 bits of zero into the OSR to align things
  push noblock      [3] // Push to FIFO
.wrap

% c-sdk {
static inline void daisychain_rx_program_init(PIO pio, uint sm, uint offset, uint datapin, uint sidesetpin) {
    pio_sm_set_consecutive_pindirs(pio, sm, datapin, 1, false);
    pio_gpio_init(pio, datapin);

    pio_sm_config c = daisychain_rx_program_get_default_config(offset);
    sm_config_set_sideset_pins(&c, sidesetpin);
    sm_config_set_in_pins(&c, datapin);
    sm_config_set_jmp_pin(&c, datapin);
    sm_config_set_in_shift(&c, true, false, 9);
    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
    sm_config_set_clkdiv(&c, 2);
    pio_sm_init(pio, sm, offset, &c);
    pio_sm_set_enabled(pio, sm, true);
}
%}

.program square_wave
.side_set 1
.wrap_target
    nop sideset 1
    nop sideset 0
.wrap

% c-sdk {
static inline void square_wave_program_init(PIO pio, uint sm, uint offset, uint pin) {
    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
    pio_gpio_init(pio, pin);

    pio_sm_config c = square_wave_program_get_default_config(offset);
    sm_config_set_sideset_pins(&c, pin);
    sm_config_set_clkdiv(&c, 5);
    pio_sm_init(pio, sm, offset, &c);
    pio_sm_set_enabled(pio, sm, true);
}
%}
Essentially:
1. Changed it to do the jump based on the Rx pin not the enable pin to do start bit validation.
2. Changed the Tx lockout to use IRQ 4 (not sure whether anything needs changing elsewhere to allow this, didn't look like it was being used anywhere).
3, Changed it to read each bit, and the flag bit, three times. Software will need to process this to do the majority voting bit.
4. Changed the timings to account for the added instructions, the two cycle error and to move the sample point to the second half of the bit to avoid the
need to invert (I think!)
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Still very surprised by the short cable lengths but looking at the data sheet again it seems to be of the right order. The calculation in 8.1.2.2.3 combined with the typical capacitances gives a cable length of a few feet which matches your result very well.

As you say, the board needs to be mounted adjacent to the battery modules. Doing this should also minimise the amount of inverter noise seen so the extra work to validate signals may not be needed?
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Pete9008 wrote: Fri May 13, 2022 5:28 pm Thant's very interesting, I would have expected it to go quite a bit further. Do you know the length limit for a modified board? What's the cable - screened twisted pair?
On my bench I'm using a tightly twisted pair with no shielding, it's exactly 1m long when twisted. It works fine if i push it into the socket on my board. However, if i join it with a 30cm molex pigtain (whether twisted or not) it fails. I don't know if it's the extra distance, or something specifically strange about the molex wire. My guess is that it was just near the limit anyway.

I haven't tested the distance with the modified board (10nF), but I'm confident that it will be dramatically more. If I compare the signal before and after the 1nF caps, it's clear that there is a significant attenuation there. I've probably spent too much time on that aspect, as it seems I already have a solution to that at least.

I have tried mangling and re-mangling the code to come up with a good way not to receive while transmitting, and ultimately went back to my original strategy, combined with a very simple false start detection. I will look more at oversampling and averaging, but for now, I'm tired :)

One other thing worth noting, despite tuning the timing offset using the sideset, I was not happy with the result. Instead I found the range of timings that worked, and chose the centre of that range, which coincides with the number I calculated yesterday.

Ultimately, I'm hoping that performance is good when I use a dramatically shorter cable in my own build.

Current version can be fond here: https://github.com/catphish/ti-daisycha ... co/bms.pio
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

The error in timing got me wondering about metastability latches, went looking and found:
There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic RW
from metastabilities. This increases input delay, and for fast synchronous IO
(e.g. SPI) these synchronizers may need to be bypassed. Each bit in this
register corresponds to one GPIO.
0 → input is synchronized (default)
1 → synchronizer is bypassed
If in doubt, leave this register as all zeroes.
So a delay of 2 clock cycles (it's not clear whether this is the system or PIO clock, would guess the later if it was just the PIO but they seem to serve the GPIOs too so could be either). Obvious really and annoyed that I forgot that they would be there! The technique is valid but the detail was missing, sorry to have wasted your time looking for a non-existent issue.

Would this explain the difference you saw when using the sideset commands?
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Pete9008 wrote: Sat May 14, 2022 11:54 am The error in timing got me wondering about metastability latches, went looking and found:
There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic RW
from metastabilities. This increases input delay, and for fast synchronous IO
(e.g. SPI) these synchronizers may need to be bypassed. Each bit in this
register corresponds to one GPIO.
0 → input is synchronized (default)
1 → synchronizer is bypassed
If in doubt, leave this register as all zeroes.
So a delay of 2 clock cycles (it's not clear whether this is the system or PIO clock, would guess the later if it was just the PIO but they seem to serve the GPIOs too so could be either). Obvious really and annoyed that I forgot that they would be there! The technique is valid but the detail was missing, sorry to have wasted your time looking for a non-existent issue.

Would this explain the difference you saw when using the sideset commands?
The difference between the eye of the signal (as measured by comparing the sideset) and the most reliable point in the signal (as measured by trialing each delay value then taking the mid point on the reliability bell-curve) is one PIO cycle (two system clock cycles). This synchronizer almost certainly explains this delay, so thank you for pointing that out!
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

I have now found what I believe is a much more serious problem with the design.

The pulled-up line is idling not at +3.3v but at +2.2v. I don't know why, but the result is that when I transmit, the levels are as follows:

* On my board: (starting from 2.2V idle) +3.3V to -3.3V (driven hard by the RS422 driver)
* On the AC coupled line: (starting from 0V idle) +1.1V to -5.5V
* (I am guessing here) On the battery module (which should idle at +5V): +6.6V to -0.5V

The final voltage is clearly going to be a problem here! See attached scope trace of the AC coupled line. The first two bytes are generated from my end, and the third from the battery in response.

Really, I need to get this line idling at a voltage much closer to +5v on my end so that it's pulled negative at the other end! :(
PXL_20220514_135003822.jpg
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Adding a 1k pull-up to 5v changes the idle level to 4.7V. The result is as one would expect, a noticeable increase in "reach". A 1k pull-up to 3.3V gives 3.11V and has a similar but MUCH less dramatic impact.

The obvious takeaway from this are that the whole system should really be running at 5v if at all possible.

I also suspect that with the 10nF capacitors, the change to 10k pull-ups was a mistake, and 1k will perform better. 1k doesn't seem to attenuate the 4MHz signal, and in fact loading the line more could be a benefit when it comes to noise?
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Interesting!

Struggling to see why it would be at 2.2V. What transceiver are you using? Also where is ground on that capture?

What's the other half of the diff pair doing? Any chance of some scope captures showing both lines at your end, on the cable and if possible at the far end?

Also had a thought about the PIO clock, the meta latches will be in the master PIO clock domain. It's very likely that all the PIO state machine registers are in that same domain too with the clock division being done using the register enable lines - makes the timing much simpler.
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Pete9008 wrote: Sat May 14, 2022 3:38 pm What transceiver are you using? Also where is ground on that capture?
What's the other half of the diff pair doing? Any chance of some scope captures showing both lines at your end, on the cable and if possible at the far end?
There is no ground on the capture posted above. This is line to line. ie just the difference between the two. The level of the line on the left is the idle state (0v line to line). I'm not sure I can get traces from inside the battery module very easily, but I will have a look if I have a chance. I will do a new set of traces now that I've put the 1k resistors back though.
The transceiver is MAX3485. Now that I actually read the datasheet properly... I can clearly see that the input impedance is 12k, so this makes perfect sense.
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Sorry, I meant where is 0V on the scope screen, is it aligned with the marker on the left? You did say it was on the AC but I'd missed it and assumed it was one of the lines on your board (which didn't make a lot of sense thinking about it again :? ).

The reason I ask is I'm wondering if you actually want it to idle at nearer 1.6v/1.4v for the two lines (just enough to keep the transceiver happy in idle). That will lead to a symmetrical signal on the AC lines which will then lead to a symmetrical signal at the receiver (it is up to the receiver to set it's biasing levels to suit its own common mode range). Given that the input thresholds for the RS3485 are a symmetrical +-200mV a symmetrical signal on the AC bus would seem to give the best signal to noise?

When I look at the above signal I see the small positive signal as being the problem and idling nearer 5V is going to make that worse isn't it?
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Pete9008 wrote: Sat May 14, 2022 4:03 pm Sorry, I meant where is 0V on the scope screen, is it aligned with the marker on the left? You did say it was on the AC but I'd missed it and assumed it was one of the lines on your board (which didn't make a lot of sense thinking about it again :? ).

The reason I ask is I'm wondering if you actually want it to idle at nearer 1.6v/1.4v for the two lines (just enough to keep the transceiver happy in idle). That will lead to a symmetrical signal on the AC lines which will then lead to a symmetrical signal at the receiver (it is up to the receiver to set it's biasing levels to suit its own common mode range). Given that the input thresholds for the RS3485 are a symmetrical +-200mV a symmetrical signal on the AC bus would seem to give the best signal to noise?

When I look at the above signal I see the small positive signal as being the problem and idling nearer 5V is going to make that worse isn't it?
Yes, 0v is the marker on the left.

Based on my observations, the bq76PL455A biases the line at +5v (or so), not at 0v. When it drives the line, it never drives it more positive than the idle state. As an outside observer, the line goes from 0v to -8v and back. To me, this suggests that I should also bias the line at my positive rail voltage, so that the low pulses I receive go well below 0v, but then the high pulses go back into the positive region. If I biased at 0v, I would never receive a signal greater than 0v. I hope that makes sense. Do tell me if I'm wrong about this though.

If I idle at 5v, the small positive increase doesn't happen. When the transmitter is enabled, the line is driven hard at +3.3V or -3.3V, so when idling at 5V, nothing happens until it's driven negative, at which point is drops from 5V to -3v3V. The step seen is when the line idles at 2V and increases to 3.3V when the transmitter is enabled.

Anyway, with the 1k resistors re-installed, and the line idling at 3.1V, here's a new grab of:
1) The line-to-line levels (no ground).
2) The positive and negative lines on the MAX3485, with 0v offset so they don't collide)
3) The same as 2, but with 0v in the same place, in case you prefer that.
In each case there's 2 bytes transmitted by me, and a third byte transmitted by the battery.

Thank you for your continued interest and assistance!
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

PS. I realise it would make much more sense if the module started with the line at 0v, and drove it alternately positively and negatively from there, avoiding DC offset, as the datasheet suggests... but I see no evidence that it works this way :(
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Does the bq76PL455A bias one line at 5v and one line at 0v or both at 5V?

What is bothering me is the change in DC bias point on the AC line when the bq starts to transmit. It just suggests to me that the two ends are biasing the line differently. May just be the way it works but it looks like on a longer message (do you even have longer messages or are they all this length) the receive thresholds may become marginal.
catphish wrote: Sat May 14, 2022 4:21 pm Thank you for your continued interest and assistance!
Vested interest - hoping to use this myself in the future ;) Plus I enjoy a challenge!
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

catphish wrote: Sat May 14, 2022 4:31 pm PS. I realise it would make much more sense if the module started with the line at 0v, and drove it alternately positively and negatively from there, avoiding DC offset, as the datasheet suggests... but I see no evidence that it works this way :(
For me the main question is what does the far end see. If the waveforms looks good there and all the messages are relatively short then it's probably good enough?
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

I'm starting to think that you've got it about as good as it's going to get with the 12k load of the transceiver. I think it would probably benefit from a higher impedance transceiver which would then allow higher impedance pull up/downs and so less pulling of the bias point when the far end is transmitting.

I'm coming round to your way of thinking that 1k pull up/down may be the best compromise but it's still making me uncomfortable!
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

May be worth trying something like the SP485R (150k input, 400 device fanout) or SN65HVD05 (256 fanout) to see if it helps. I might try one of these when I get round to building up a board.
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Thanks again! Just to clarify for anyone reading, this is how I currently have things configured:
Screenshot at 2022-05-14 18-04-31.png
I feel like I'm missing something really fundamental here, because looking at the way the bq76PL455A transmits, it never drives the line more positive than the idle state, but this seems mad for a capacitively isolated line. The data sheet says they use manchester encoding to eliminate DC bias, and yet I can clearly see that they create a DC bias by starting the transmission with a -10v transition instead of a -5v transition. This is annoying because during a transmitted byte, this offset gradually eliminates itself. It's much more visible on the battery end which has a 1nF capacitor, vs my end which is much stronger with its 10nF. I just wish I could understand why it's designed this way, or if I'm missing something!

Right now it's working over a very dodgy 2m line made up of a twisted cable, a pigtail, and some crocodile clips. I'm still really hoping that all the small improvements I make here will pay off once I put it in a vehicle with a short screened cable and lots of electrical noise!

For a future revision, I really think it will be worth trying to use a 5V transceiver.
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Agree, not what I would expect either. Have you looked at the signals on the link between two bq76 boards just in case that's any different?

Still interested in seeing a plot of the bq76 end if you happen to have the scope on it at some point in the future.
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Pete9008 wrote: Sat May 14, 2022 4:34 pm What is bothering me is the change in DC bias point on the AC line when the bq starts to transmit. It just suggests to me that the two ends are biasing the line differently. May just be the way it works but it looks like on a longer message (do you even have longer messages or are they all this length) the receive thresholds may become marginal.
By the way, without any interference from my hardware, ie just an oscilloscope connected directly to the battery, this is what it transmits! I'd go as far as to suggest that this is a design error, as there is very clearly a DC bias there.

The drift towards 0v is quite subtle here, as the only load on the line is my scope.

Edit: it occurs to me that the DC bias is probably a good way to avoid noise causing false starts. By idling at +5v, it takes a much bigger noise spike to generate a negative start bit.
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

In conclusion, I think this implementation is the best that can be done at 3.3v. However, running it at 5v provides 2 big benefits.
1) The incoming pair of signals will sit correctly between 0v and 5v (starting at 5v, and the diodes preventing drift). This will likely reduce noise on RX.
2) The output signal will be much stronger (reaching +5v and -5v at the other end rather than the current +5v and -1.4v). This will hugely reduce noise on TX.
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

I think it's fine and you are right, 5V would be better.

Think of the ideal whole system starting in the idle state and then running through a couple of bits:
TXH TXL Bus RXH RXL DiffV
Idle +5V 0V 0V +5V 0V +5V
1st half bit 0V +5V -10V 0V +5V -5V
2nd half bit +5V 0V 0V +5V 0V +5V

i.e. full differential signal swing produced at the receiver.

This will continue over the message as long as there is no DC content to the message so Manchester encoding needed.
There will be a slow drift due to the bias resistors but as long as RC (R is the transceiver load impedance, C is the coupling capacitance) is long compared to the message time and short compared to the inter-message time it's not an issue.

You're getting two issues, the first due to the 3V3:
TXH TXL Bus RXH RXL DiffV
Idle +3V3 0V 0V +5V 0V +5V
1st half bit 0V +3V3 -6V6 1.7V +3V3 -1V7
2nd half bit +3V3 0V 0V +5V 0V +5V

So a reduction in signal level.

Second because of the low impedance of the transceiver you need low value bias resistors. Combined these produce a low R seen by the bus which leaves RC on the low side compared to message length - but probably good enough.

Does that make sense?

Edit - think our posts crossed!
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Re: New BMS for bq76PL455A based batteries

Post by catphish »

Pete9008 wrote: Sat May 14, 2022 5:55 pm Does that make sense?

Edit - think our posts crossed!
Yes :) I think we've reached the same conclusion.

Do you have any idea how we might be able to drive the bus at 5v without blowing up the RP2040? My board already has a +5v power supply (actually 4.5v but easily increased), so it should just be a matter of level shifting.
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Re: New BMS for bq76PL455A based batteries

Post by Pete9008 »

Probably something like a SN74LVT1T34 for the Rx line (or similar, not my first choice but they were all that was in stock when I checked a few weeks ago). For the Tx and enable you'll probably find that the Pico 3V3 high level is fine, let me find the datasheet.
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