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Re: Toyota Auris and Yaris Inverter Logic board
Posted: Tue Oct 06, 2020 6:12 pm
by bexander
Thank you for your help, Johannes and Damien, to conclude this! Will report back when the STM32 is replaced, programmed and tested.
Good suggestion SRFirefox. I bought some "ChipQuik SMD removal kit". I'll try that first, but if that is unsuccessful I might use the knife.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Thu Oct 08, 2020 7:49 am
by bexander
I have now replaced the stm32, reprogrammed it and tested. The spikes in angle plot is still there... I don't know whats wrong or what I'm doing wrong but this is beyond me??
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Thu Oct 08, 2020 9:35 am
by bexander
When doing an AC-measurement on C27 and C28 I see a disturbance at 8,8kHz and up to 20mV peak. Amplitude and sign varies with the adjustment of the input voltage at the resolver input. I'm feeding in dc-voltages and using SinCos as encoder setting. The disturbance is for a set input the same sign.
What is running at 8,8kHz on the board? I'm running inverter at 4,4kHz and resolver exciter is not active in SinCos encoder mode.
How can I calculate the time a certain number of data points corresponds to in the angle plot?
EDIT:
When I inhibit PWM by removing my 5V supply to R38 the disturbance is gone on the scope. However the angle output is also stopped. Any way I can inhibit PWM but still get angle output?
EDIT2:
A picture from scope, probe at C27.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Thu Oct 08, 2020 1:52 pm
by bexander
As I'm running on bench in manual mode I don't have any PWM output. And also no change in disturbance frequency when changing PWM frequency.
I've been trying to probe around on the board but still can't find anything creating this signal.
Also, as mentioned before, no exciter output either, as expected, but what else is running at 8,8kHz on the board?
EDIT:
I probed all pin on the stm32.
On pin 61 which is NC but still outputs a signal at 17,7kHz, twice what I'm looking for.
Also at pin 14 I found this.
Why is there so much disturbance on a signal going to GND via a resistor with the exact frequency I'm searching for?
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Fri Oct 09, 2020 5:20 pm
by bexander
I get the same behavior at the ADC inputs when running the SW on my blue pill. I have tried different sources of 3,3V for this setup and the result are the same. I think there is a problem in the SW and how the clocks and ADC are setup? I know to little about this micro controller to have any usefull input but the disturbance I can see is at 8,8kHz and goes away if the MG2_PWM_INHIBIT is high.
Any comments on this? Is this possibly a SW issue?
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Fri Oct 09, 2020 10:32 pm
by johu
So keep in mind the software runs on numerous devices with resolver and doesn't play up. Please check on github in param_prj.h which version still shows the raw "sin" and "cos" inputs. It was one of the early FOC versions.
Regarding your findings: you discovered the pin that normally generates the PWM for the comparator reference (over current protection). That comparator is not present on the Prius board but the PWM runs anyway.
Also the control loop frequency is always 8.8 kHz regardless the PWM frequency. So you're seeing the ADC sampling but little blips of 20mV will not cause a large angle swing.
When you shut down PWM, the sampling also stops, thats why it looks clean then. Currently I have no idea, I think a software with sin and cos display hopefully reveals the problem.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 5:28 am
by bexander
johu wrote: ↑Fri Oct 09, 2020 10:32 pm
So keep in mind the software runs on numerous devices with resolver and doesn't play up. Please check on github in param_prj.h which version still shows the raw "sin" and "cos" inputs. It was one of the early FOC versions.
Regarding your findings: you discovered the pin that normally generates the PWM for the comparator reference (over current protection). That comparator is not present on the Prius board but the PWM runs anyway.
Also the control loop frequency is always 8.8 kHz regardless the PWM frequency. So you're seeing the ADC sampling but little blips of 20mV will not cause a large angle swing.
When you shut down PWM, the sampling also stops, thats why it looks clean then. Currently I have no idea, I think a software with sin and cos display hopefully reveals the problem.
I'm just trying to find out why I have spikes in the angle plot signal. I'm under the impression that the angle signal should move max 1 degree or so and I see spikes in ranges of 10 degrees. Should I just ignore the spikes and move on? Have I created a problem that is not there due to me misunderstanding what should and should not be ok? Would you say that the spikes in angle is not a problem?
The reason I started to dig into this is because I'm having trouble finding the syncofs value and it then came to my attention that the spikes in angle plot should not be there.
Side note: It does not mean that everyone is experience a problem even though the problem might be there? I find it very odd that I see the same behavior on two very different HW. Almost the only thing the Yaris board and the Bluepill has in common is the SW.
I'm not able to find any SW with the sin and cos param lines not commented out in the param_prj.h? Or have I been looking for the wrong thing?
/* VALUE_ENTRY(sin, "°" ) \
VALUE_ENTRY(cos, "°" ) \*/
I'm agreeing that the 20mV dips on the ADC signal can not be the cause of a 10 degree fluctuation in the angle, when doing the math of how angle is calculated. But question remains, what then can be the cause of the spikes?
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 7:25 am
by Jack Bauer
Again, we can rule out a design issue as I and others have used this rev of board without problem. Ditto software. So that leaves the particular board you have. I see you have ordered another which I will ship this week so suggest park it until the new board arrives. If it displays the same issue then we can dig deeper. It's easy to go down a rabbit hole with these things. Don't ask me how I know:)
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 7:41 am
by bexander
But why do I have the same issue with spikes in the angle plot when I run the SW on another board, my blue pill? In my opinion, that suggests it is not the board itself?
Do we all agree that the spikes in the angle plot should not be there and you have not seen them in any of your working boards?
Yes, I'm starting to lose my sanity over this so I will take your advise and park this until the new board arrives. You can dissregard the e-mail I sent.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 8:08 am
by johu
bexander wrote: ↑Sat Oct 10, 2020 7:41 am
But why do I have the same issue with spikes in the angle plot when I run the SW on another board, my blue pill? In my opinion, that suggests it is not the board itself?
Yes. Could it be your power supply? Are you running a sufficient amplitude into the sin/cos pins? The calculation at some point calculates the quotient sin/cos so if both are small amplitude the SNR decreases.
bexander wrote: ↑Sat Oct 10, 2020 7:41 am
Do we all agree that the spikes in the angle plot should not be there and you have not seen them in any of your working boards?
Absolutely, +/-1° is pretty much the most you should see. Like that little noise floor between the blips.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 8:31 am
by johu
Did some plotting myself.
So with my test setup I'm also getting about 5° jitter. The supply voltage (blue) looks pretty clean (10mV/div) and I'm getting the same blips at 8.8 kHz. I'd say you can roll with that.
EDIT: I will check the angle jitter later in Touran. It has a newer V3 mainboard with the 1 nF filter caps very close to the processor pins. That is also important for you Blue Pill setup to have some capacity close by.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 9:09 am
by bexander
johu wrote: ↑Sat Oct 10, 2020 8:08 am
Yes. Could it be your power supply? Are you running a sufficient amplitude into the sin/cos pins? The calculation at some point calculates the quotient sin/cos so if both are small amplitude the SNR decreases.
Unlikely, since I have tested with two different power supplies. I have also tested with different signal input levels.
I will make new tests when the new board arrives.
EDIT: My blue pill setup is far from good, done on a "non solder" experimental board.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sat Oct 10, 2020 9:32 am
by bexander
If I understand the math done in SW correctly it would require a pulse of 150mV to get a fault of 5 degree in angle.
Only the spikes I measured at Pin 14 are in this magnitude. This pin is pulled high to 3,3V on the PCB.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sun Oct 11, 2020 4:51 am
by bexander
johu wrote: ↑Sat Oct 10, 2020 8:31 am
Did some plotting myself.
So with my test setup I'm also getting about 5° jitter. The supply voltage (blue) looks pretty clean (10mV/div) and I'm getting the same blips at 8.8 kHz. I'd say you can roll with that.
I'm afraid I can't let this problem go, it bothers me to much, so please bare with me.
When searching in the datasheet for the STM I can conclude that there might be a current draw of up to +-1uA when the ADC is used and has an internal resistance of 1kohm. This means, with an external resistance of 10kohm, a total of 11kohm and 1uA. That's 11mV in worst case. The pulses observed are in range of 25mV, which I find odd.
Is the ADC read only once every "control loop turn" i.e. at 8,8kHz?
Also to get the spikes magnitudes seen in angle plot it would require a magnitude of 100-150mV. This can be observed at pin 14, also possible to connect to ADC...? Pin 14 is pulled high to 3,3V via an external 1kohm resistor. To get a voltage drop of 100mV requires 100uA.
In the schematics this pin in annotated "MG2_UVLO_IN_14". If this pin truely is an input, why is there a 100uA current draw every "control loop turn" on this pin?? It makes no sens to me. I'm thinking that something is set as an low output for a short period of time.
I'm stuck on the idea that there is something going on internaly in the uC that causes the spikes seen in angle plot. Since I have tested it on three uC and Johannes also can see similar results it is not just a coincidence. Even if this may or may not have a large effect on the performance of the inverter it is still worth looking into unexplained behaviors. I'm not a programmer so I really struggle understanding where to look in the SW for clues so any pointers on where to start looking is much appreciated.
Re: Toyota Auris and Yaris Inverter Logic board
Posted: Sun Oct 11, 2020 5:02 am
by arber333
Is it possible there is a Led connected to pin14 via different pin? If that LED would be blinking something has to draw current through pull up.
Re: Large jitter on angle in resolver and sincos mode
Posted: Sun Oct 11, 2020 9:59 am
by johu
Ok, will help researching. Also didn't find a version with sin/cos so just added it to the recent firmware.
Yes sin/cos is sampled once every 125µs in a one shot fashion. All other values are continuously sampled
Re: Large jitter on angle in resolver and sincos mode
Posted: Sun Oct 11, 2020 11:28 am
by bexander
To be clear, the control loop runs at 8,8kHz or approx 114us and the ADC samples sin/cos input at 8,0kHz or 125us. Is this correct?
If so, it would further strengthen that something in control loop is drawing current and not the ADC sampling as the disturbance seen on ADC inputs are at 114us appart.
Re: Large jitter on angle in resolver and sincos mode
Posted: Sun Oct 11, 2020 6:06 pm
by bexander
After looking around in the SW. In hwinit.cpp there is a funtion detect_hw which does a is_floating(GPIOA, GPIO0), thats pin 14 on the Yaris board.
Is this function run once at startup or every control loop?
I can't figure out which is the "main" program file? so don't know when this is called.
When looking at the voltage measurement from johu it is according to my math possible to get a voltage change of 25mV/250us from a 1nF capacitor using a 30k resistor. That is the fast voltage change (dip) and then recharge (rise) via 10k and 1nF in ~40us.
And also a voltage division between external 1k resistor pullup and 30k to gnd will result in a dip of 106mV.
Just saying it might be possible to cause this behavior using a 30k pullup/pulldown resistor.
Re: Large jitter on angle in resolver and sincos mode
Posted: Mon Oct 12, 2020 9:22 am
by bexander
I have tested with the new SW an the "blue pill" and there are spikes in either sin or cos or both matching the spikes in angle, as one could expect.
Sidenote: The sine signal is the one inputed to PA7 and cos is inputed at PA6 without any pinswap selected. According to Damiens schematics (Prius and Yaris boards) it is the other way around.
Re: Large jitter on angle in resolver and sincos mode
Posted: Tue Oct 13, 2020 5:45 pm
by bexander
What is the ADC clock frequency? I can't find where the prescaler for this is set. Is it at max of 14MHz or is it lower?
Now time for speculation:
In hwinit.cpp is_floating(GPIOA, GPIO0) is done once at startup?
This sets PA0 to pullup/down and should leave the pin as gpio_clear, which sets the pin in pulldown, right?
Then in inc_encoder.cpp PA0 is used as a dummy pin to avoid noise during adc_injection.
Here PA6 and PA7 are set gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6 | GPIO7) but not PA0. Is PA0 still in input_pulldown?? i.e. it pulls down for 1,5 Fadc clock cycles and causing the spikes on this pin and on the other two pins, PA6 and PA7?
Re: Large jitter on angle in resolver and sincos mode
Posted: Tue Oct 13, 2020 6:12 pm
by bexander
Or maybe it is not a SW issue after all... I have found some interesting info on the ADC and that the input filter 10kohm/1nF might have to high impedance. I will make measurements on this and report back. Probably have time on thursday for this.
ADC clock frequency effects what impedance can be used.
Re: Large jitter on angle in resolver and sincos mode
Posted: Tue Oct 13, 2020 8:52 pm
by johu
Not a bad guess about that PA0 pin, didn't pay too much attention.
is_floating is only called once at startup.
Re: Large jitter on angle in resolver and sincos mode
Posted: Wed Oct 14, 2020 7:10 am
by Jack Bauer
Bexander, I am sending you a fully built and working board. Its the one I used in the FOC tuning video and in a recent video running an MGR. Let's see if this solves your problems.
Re: Large jitter on angle in resolver and sincos mode
Posted: Wed Oct 14, 2020 8:06 am
by arber333
johu wrote: ↑Tue Oct 13, 2020 8:52 pm
Not a bad guess about that PA0 pin, didn't pay too much attention.
is_floating is only called once at startup.
This PA0 pin caused me much grief when using my hybrid rev2 to rev3 board! Finally i cut the trace which i had connected to OR circuit according to rev2 schematic. That stopped strange OC limit error on start signal.
Re: Large jitter on angle in resolver and sincos mode
Posted: Wed Oct 14, 2020 8:14 am
by johu
So here is a firmware where PA0 is configured as analog input in resolver/sincos mode. Please check, I will do the same.
@Arber: yes on Rev2 board PA0 was connected to the AND tree that triggered the timer disable pin. On Rev3 it no longer is and I think Damien isn't using it either. It should just be floating.